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[세미나: 7월 1일(금), 오후 4시]  Cisco Systems, 이태규 박사

Title

Electronic Packaging in the Telecommunication sector and Low melting temperature solder interconnect thermo-mechanical reliability 

Speaker

Technical Leader, Technology and Quality (TnQ) group, Packaging and interconnect technology team (PITT), Cisco Systems, 이태규 박사

Education

- Ph.D. University of California, Berkeley, Materials Science and Engineering, 2004

- M.S. Inha University, Incheon, Korea, Metallurgical Engineering, 1996

- B.A. Inha University, Incheon, Korea, Metallurgical Engineering, 1994

Professional experiences

- 2021-current, Technical Leader, Technology and Quality (TnQ) group, Packaging and interconnect technology team (PITT), Cisco Systems, San Jose, CA

- 2015-2021,  Associate Professor, Department of Mechanical and Materials Engineering, Portland State University, Portland 

- 2008-2015,  Sr. Manufacturing Engineer, Component Quality and Technology Group, Technology and Quality Group, Cisco Systems Inc., San Jose

- 2006-2008, Reliability Engineer, Component Quality and Technology Group, Technology and Quality Group, Cisco Systems Inc., San Jose

- 2004-2006, Post-Doctoral Fellow, University of California, Berkeley, Department of Materials Science and Engineering

- 1999-2004, Graduate Student Researcher, Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley

| Date | Friday, July 1st, 2022

| Time | 16:00 ~ 

| Venue | 33동 125호 (WCU 다목적실)

[Abstract]

Modern electronics require miniaturized but more complex configuration devices with higher power and higher density interconnects, consequently, an increasing number of chips and functionality in a given substrate. Heterogeneous integration through System-in-Package (SIP) and recent development in Co- Package Optics (CPO) can leverage these requirements of packaging technology to create multiple functions associated with a system or subsystem. Associated with these complex devices, temperature variations and thermally induced stresses could cause the interconnect reliability degradation, and eventually compromise the functionality of the whole packaging assembly. Along with the functionality, a package needs an increase in substrate and body size, which poses a constant challenge to the board assembly process due to package warpage. As a possible solution to these challenges, Low melting temperature solder (LTS) interconnects are of considerable interest and development. However, low melting temperature Sn-Bi system show a few performance challenges, which can be a deterrent for its use in electronics device interconnects. Sn-Bi eutectic microstructure are similar to Sn-Pb eutectic but have different damage accumulation mechanism due to Bi crystal lattice with a Rhombohedral A7 unit cell structure, which is less ductile compared to Sn-Pb, where Pb has face centered cubic crystal lattice. The nature of less ductility in Sn-Bi alloy system reveals a different damage accumulation process during thermal cycling and mechanical shock compared to Sn-Ag-Cu solder material. This presentation will cover the electronic packaging trend in the telecommunication sector along with low melting temperature solder interconnect application as a possible solution. To identify the degradation mechanism in Sn-Bi interconnects, a series of microstructure analysis were performed on thermo-mechanically stressed components. The correlation between crack initiation, crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and Electron?backscattered diffraction (EBSD) imaging. The analysis revealed the potential damage accumulation process in Sn-Bi solder joint under thermal cycling and mechanical shock, which will be presented and discussed. 

| Host | 최인석 교수(02-880-1712)