Seminar & Colloquium
[세미나: 5월 22일(수), 오전 10시 30분] Prof. Yong-Young Noh, POSTECH
Title
Development of high-performance p-type semiconductors for transistors
Speaker
Prof. Yong-Young Noh, Department of Chemical Engineering, Pohang University of Science and Technology (POSTECH)
* Education
- 2005 Ph. D. in Materials Science and Engineering, GIST, Gwangju, Korea
- 2002 MS in Materials Science and Engineering, GIST, Gwangju, Korea
- 2000 BS in Chemical Engineering, Dongguk University, Seoul, Korea
* Professional Experience
- 2013. 03. ~ 2019. 01. Associate Professor, Department of Energy and Materials Engineering, Dongguk University, Korea
- 2009. 09. ~ 2013. 02. Assistant Professor, Department of Chemical Engineering, Hanbat National University, Korea
- 2008. 01. ~ 2009. 08. Senior Research Fellow, Conv. Comp. & Mater Lab, ETRI, Korea
- 2005. 09. ~ 2007. 12. Postdoctoral Associate, Cavendish Lab, Department of Physics, University Cambridge, UK. Supervisor: Prof. Henning Sirringhaus
| Date | Wednesday May 22nd , 2024
| Time | 10:30 ~
| Venue | 33동 222호(동부 세미나실)
[Abstract]
Developing high-mobility p-type semiconductors that can be grown using silicon-compatible processes at low temperatures, has remained challenging in the electronics community for the integration of complementary electronics with the well-developed n-type counterparts. In this presentation, I will talk on our recent progress in developing high-performance p-type semiconductors as channel materials for thin film transistors. For the first part of my talk, I present an amorphous p-type semiconductor composed of selenium-alloyed tellurium in a tellurium sub-oxide matrix, demonstrating its utility in high-performance, stable p-channel TFTs, and complementary circuits [1]. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of ~15 cm2 V-1 s-1 and on/off current ratios of 106~107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient aging. Next, I present high-performance tin (Sn2+) halide perovskite transistors. [2.3]. I will mainly address inorganic perovskite thin-film transistors with exceptional performance using high-crystallinity and uniform cesium-tin-triiodide-based semiconducting layers The optimized devices exhibit high field-effect hole mobilities of over 50 cm2 V−1 s−1, large current modulation greater than 108, and high operational stability and reproducibility [4]. In addition, we explore triple A-cations of caesium-formamidinium-phenethylammonium to create high-quality cascaded Sn perovskite channel films. As such, the optimized TFTs show record hole mobilities of over 70 cm2 V−1 s−1 and on/off current ratios of over 108, comparable to the commercial low-temperature polysilicon technique level. [5]
References
[1] A. Liu, Y.-Y. Noh, et al, Nature, https://www.nature.com/articles/s41586-024-07360-w (2024)
[2] A. Liu, Y.-Y. Noh, et al, Nature Electronics 5, 78-83 (2022)
[3] H. Zhu, Y.-Y. Noh, et al, Nature Electronics 6, 650-657 (2023)
[4] A. Liu, Y.-Y. Noh, et al, Nature Electronics 5, 559-571 (2023)
| Host | 강기훈 교수(02-880-7189)