Seminar & Colloquium
[세미나: 3월 29일(금), 오후 4시] Prof. H.-S. Philip Wong, Department of Electrical Engineering, Stanford University
Title
Device Technologies for N3XT 3D MOSAIC System Integration
Speaker
Prof. H.-S. Philip Wong, Department of Electrical Engineering, Stanford University
* Biography
H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University. He joined Stanford University as Professor of Electrical Engineering in 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center. From 2018 to 2020, he was on leave from Stanford and was the Vice President of Corporate Research at TSMC, the largest semiconductor foundry in the world, and since 2020 remains the Chief Scientist of TSMC in a consulting, advisory role. He is a Fellow of the IEEE and received the IEEE Andrew S. Grove Award, the IEEE Technical Field Award to honor individuals for outstanding contributions to solid-state devices and technology, as well as the IEEE Electron Devices Society J.J. Ebers Award, the society’s highest honor to recognize outstanding technical contributions to the field of electron devices that have made a lasting impact. He is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems and served as the faculty director of the Stanford Nanofabrication Facility – a shared facility for device fabrication on the Stanford campus that serves academic, industrial, and governmental researchers across the U.S. and around the globe, sponsored in part by the National Science Foundation. He is the Principal Investigator of the Microelectronics Commons California-Pacific-Northwest AI Hardware Hub, a consortium of over 40 companies and academic institutions funded by the CHIPS Act. He is a member of the US Department of Commerce Industrial Advisory Committee on microelectronics.
| Date | Friday March 29th , 2024
| Time | 16:00 ~
| Venue | 42-2동 B101호
(30동 맞은 편 새로 생긴 데이터 사이언스 대학원 건물 https://naver.me/Gpfrdt1Z)
[Abstract]
Future electronic systems will continue to rely on, and increasingly benefit from, the advances in semiconductor technology as they have had for more than five decades.
Three dimensional integration is one of the major technology directions for integrated circuits. Nanosystems of 3D integrated “X” technology (N3XT) is a key concept at the chip level, where X can be memory, photonics, spintronics, power electronics, nanomechanics, sensors and actuators, and RF/mm-wave. We must also go beyond a single chip from a wafer and focus on integrating chips into systems using MOSAIC (MOnolithic Stacked Assembled IC). I will give an overview of the new materials, device technologies, and design concepts that may need to be developed to realize this vision, focusing on memory logic integration for energy-efficient computing systems.
References:
[1] S. Liu … H.-S. P. Wong, “Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development,” IEDM paper 39.1 (2023)
[2] S. Li … H.-S. P. Wong, S. Mitra, “High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/μm at VDS of 0.75 V by self-aligned doping in sub-20 nm spacer,” IEDM paper 10.6 (2023)
[3] K. Akarvardar, H.-S. P. Wong, “Technology Prospects for Data-Intensive Computing,” Proceedings of the IEEE, vol. 111, Issue 1, pp. 92 – 112 (2023)
[4] H.-S. P. Wong et al. "A Density Metric for Semiconductor Technology," Proceedings of the IEEE, vol. 108, no. 4, pp. 478-482, April 2020.
| Host | 김상범 교수(02-880-7359)