Seminar & Colloquium
[세미나: 2월 3일(금), 오전 10시 30분] IBM, 최기식 박사
Title
Advanced Interconnect Technology in the era of Heterogenous Integration
Speaker
최기식 박사, Manager, Interconnect Integration, IBM Research
Biography
Kisik Choi, Ph.D. has been leading advanced interconnect integration team at IBM Research at Albany, New York since 2017 with responsibility of developing innovative interconnect technologies for MOL & BEOL of advanced logic nodes beyond 3 nm. His team is working on sub-20 nm pitch advanced patterning, alternative materials of Cu, and innovative interconnect schemes for ultimate scaling solutions.
Prior to joining IBM, Dr. Choi was Research Fellow / V.P. at SK Hynix in Korea. During his 3-year tenure at SK Hynix, he developed critical HKMG technologies for peripheral circuits of DRAMs and later he led a development team which successfully delivered 28nm Logic technology with RMG. Prior to joining SK Hynix, he was a manager at Globalfoundries and high-k/metal gate expert in the research alliance based in IBM’s T. J. Watson Research Center and contributed to the serial development of IBM alliance’s advanced logic technologies including 10nm finFETs.
He was a recipient of IEEE EDS George E. Smith Award in 2013 by his coauthored work about HKMG. Right before he joined IBM in 2016, the body of HKMG work he contributed as a key alliance member was recognized as IBM Research’s Extraordinary Accomplishment. He received IBM’s Outstanding Technical Achievement Award in 2018.
He is a senior member of IEEE. He served as a committee member for AVS ALD conference (2007-2010) and a committee chair of Device Technology Session of SEMICON Korea Technology Symposium (2014-2016). He reviewed multiple journals and proceedings papers (VLSI, IEDM, APL, EDL, JVST). He has authored or co-authored +90 publications and +100 patents.
Dr. Choi received his M.S./B.S. degree in Materials Science and Engineering from Seoul Nation University and Ph.D. degree in Electrical & Computer Engineering from Texas Tech University.
| Date | Friday, February 3rd, 2023
| Time | 10:30 ~
| Venue | 33동 125호 (WCU 다목적실)
[Abstract]
As the pace of the conventional semiconductor scaling slows down due to the mounting challenges arising from the nanometer scale feature sizes, the industry is seeking for breakthroughs to continue PPA (power, performance, area) improvement from the 3D-integration of the chip level and advanced packaging of multiple heterogenous integrated semiconductor dies. The conventional BEOL interconnect is also benefited by this industry trend of three-dimensional integration with disaggregation while it continues to address various challenges in RC delay reduction and reliability associated with pitch scaling. For instance, the backside of a wafer became accessible thanks to wafer bonding and thinning technology and the BSPDN (backside power distribution network) is being investigated actively by the industry. When the power rails are separated from the signal lines and moved to wafer backside, significant benefits in design efficiency and device performance can be achieved. In this talk, various aspects of the BSPDN scheme will be discussed in conjunction with the conventional scaling technologies for frontside interconnect. 3D integration of the functionality elements to BEOL such as embedded memories and innovative switching devices is the other important approach to reduce footprint and increase the computing speed especially for AI (artificial intelligence) applications.
Continued innovations in BEOL scaling, backside processing and functional BEOL elements will be implemented either collectively or complementarily to meet the demands for advanced devices and systems. For future devices beyond conventional CMOS, we need to expand the concept of the interconnect as an active building block for the advanced packaging and 3D integration because the improved performance and built-in flexibility in each chip will eventually provide freedom to the overall system design optimization.
| Host | 김상범 교수(02-880-7359)